Overview
- Researchers built three stacked silicon device layers with 625 transistors per layer and reported device yields of 98–100 percent.
- The process moves ultrathin single-crystal silicon nanomembranes onto finished circuitry using a roll laminator and requires bonding temperatures no higher than 200°C.
- Devices made this way show output current densities comparable to bulk silicon and outperform prior low-temperature monolithic approaches by roughly three to four times.
- The team says the method is scalable beyond three layers and is preparing technology transfer and foundry validation with industry partners including IBM, Intel and TSMC.
- If adopted at scale, the approach could pack far more vertical interconnects into chips to boost compute density and energy efficiency for workloads such as AI, but commercial integration will require foundry-scale demonstrations and packaging and thermal validation.