Overview
- TSMC plans a U.S. packaging site in Arizona by 2029 with CoWoS, which places multiple chiplets on a silicon interposer, and 3D‑IC, which links chips in vertical stacks to boost speed and bandwidth.
- TSMC will delay ASML’s high‑numerical‑aperture EUV machines until at least 2029 due to per‑tool costs above €350 million and will keep improving its existing EUV lines instead.
- The company is holding capital spending near $56 billion and says expected returns support that outlay, as it maintains gross margins of about 56%.
- TSMC expanded work with Synopsys and extended its Cadence partnership to speed certified design flows and silicon IP for next‑generation AI chips.
- Analysts and market voices have been upbeat on the strategy, with TV host Jim Cramer calling TSMC “a very good situation” after the company reported a solid quarter.