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4w ago

TSMC and Taiwan Researchers Build MoS2 Transistor With 0.42 nm Engineered Interface

Engineering a 0.42 nm aluminum‑oxide buffer on monolayer MoS2 produces about 1 nm equivalent oxide thickness, showing strong lab transistor metrics with wafer‑scale manufacturability still unproven.

Via memeburn.com
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Overview

  • Researchers from TSMC Corporate Research and National Yang Ming Chiao Tung University reported in Nature Electronics a lab demonstration of a top‑gate transistor built on CVD‑grown monolayer MoS2 with a 0.42 nanometre epitaxial aluminium‑oxide interface.
  • The team formed the buffer by depositing an ultrathin epitaxial aluminium layer on MoS2 and oxidizing it, then adding a high‑κ hafnium oxide gate dielectric to create a stack that behaves like ≈1 nm equivalent oxide thickness.
  • Devices showed low leakage current, minimal hysteresis, and peak transconductance of about 0.45 mS/μm for roughly 100 nm channel lengths, indicating improved gate control without sacrificing carrier transport.
  • The fabrication used chemical vapor deposition for MoS2 and standard deposition/oxidation plus high‑κ steps that do not require wholly new equipment classes, but uniformity, yield, reliability, and full fab integration remain unresolved for mass production.
  • The result reframes scaling challenges by treating the semiconductor/dielectric boundary as an active design element and could steer future chip designs toward atomic‑scale interface engineering rather than only new bulk materials.