Overview
- Rapidus announced a per-wafer target of ¥3 million–¥3.5 million, roughly $18,500–$21,600, which the company says undercuts industry reports of about $30,000 per wafer for TSMC’s 2nm node.
- The company reiterated a plan to begin high-volume manufacturing in the second half of 2027 and said it expects meaningful volumes only in 2028 after months of yield learning at its IIM-1 fab.
- Rapidus said it is negotiating with more than 60 potential customers as it seeks overseas design wins, but those talks do not mean it has proven production-level yields or long-term contracts.
- Industry analysts point to TSMC’s roughly 72–73% foundry share and its Open Innovation Platform of silicon-proven IP, EDA flows and packaging partners as major barriers that pricing alone will not overcome.
- Major risks to Rapidus’s plan include unproven large-scale yields, the slower economics of single-wafer tool utilization, exchange-rate and profitability pressures, and the time needed to build a design ecosystem that customers trust.