Overview
- This week Peking University released a prototype electronic design automation tool built for Huawei’s LogicFolding that treats a multilayer chip as a single 3D design space.
- University tests on open-source circuits reported about a 30% cut in internal wire length and improved thermal and performance metrics, but those results are early and limited to prototype cases.
- Huawei has formalized the approach as the Tau Scaling Law and says Kirin smartphone chips using LogicFolding are planned for later in 2026 and it aims for 1.4nm‑equivalent performance by 2031.
- Independent analysts and industry players caution major hurdles remain, including maturing commercial EDA toolchains, integrating foundry process kits, managing heat and power in stacked designs, and proving production yields.
- TSMC and others say the industry is already shifting toward energy efficiency, advanced packaging and chip stacking for AI workloads, so Huawei’s effort fits a wider move but does not yet change the balance of global fabrication capabilities.