Overview
- PCI-SIG made the PCIe 8.0 draft 0.5 available for members to review, marking the first full specification draft that locks core architecture targets.
- PCIe 8.0 sets a 256 GT/s signaling rate and up to 1.0 TB/s of bi-directional bandwidth over a 16‑lane link, which is eight times PCIe 5.0.
- The draft adopts PAM4 signaling, which uses four voltage levels to move more data per cycle, with forward error correction and Flit Mode to keep reliability and latency within targets.
- The group is evaluating new connector designs because traditional edge connectors and PCB traces face severe signal loss and crosstalk at 256 GT/s, while preserving backward compatibility remains a priority.
- Vendors can begin early prototypes now, with the spec aimed at data-heavy uses such as AI and cloud servers and a roadmap that targets final ratification in 2028.