Overview
- Hardware leaker Jaykihn, cited by Wccftech and TweakTown, describes Big Last Level Cache variants with up to 288 MB of L3 on dual‑tile chips and 144 MB on single‑tile parts, which could keep more data on chip and cut trips to system memory.
- The reported flagship uses a dual‑compute‑tile design with 52 total cores made up of 16 performance cores, 32 efficiency cores, and 4 low‑power efficiency cores.
- TweakTown reports a shift to a shared L2 cache for small clusters of two performance cores with 4 MB per cluster, a change meant to reduce ring‑bus stops compared with today’s private per‑core L2 design.
- The leaker also points to new enthusiast labels, with single‑tile cache‑heavy models branded as “D” and dual‑tile versions as “DX.”
- Wccftech lists a broad Core Ultra Series 4 desktop lineup from 35 W to 175 W, including a 65 W 22‑core bLLC option with 108 MB of L3, though all specifications remain unconfirmed until Intel provides official details, potentially at Computex in June.