Overview
- KAIST announced Friday that researchers built a programmable dynamic memtransistor (PDM) and a fabricated PDM array and reported lab results showing as much as a 40-fold drop in prediction error on signals that mix fast and slow changes.
- The PDM uses a dual-layer transistor design with a charge-storage layer that processes incoming signals and an electron-trapping layer that nonvolatilely controls how fast the device recovers to its baseline.
- In experiments the team tuned current recovery time across about a fivefold range and shifted the device's characteristic frequency by more than tenfold, enabling on-chip matching to different input timescales.
- A prototype PDM array achieved accuracy comparable to conventional software-based processing while consuming far less energy, because programmed response states are retained without continuous power.
- The work, published in Nature Communications with Samsung Semiconductor co-authors, uses materials compatible with standard manufacturing but remains at the prototype stage and will need scale-up, yield testing, long-term reliability checks, and field trials before commercial deployment.