Overview
- Multiple outlets citing leaker Jaykihn report Nova Lake desktop chips with Big Last Level Cache variants up to 288 MB of L3 in dual‑tile designs and 144 MB in single‑tile parts.
- The rumored flagship uses two compute tiles for 52 cores in total, pairing 16 performance cores with 32 efficiency cores and 4 new low‑power E‑cores.
- The leak describes a major shift to a shared L2 setup that clusters two P‑cores around a 4 MB L2 to cut ring‑bus stops, trading away Arrow Lake’s 3 MB private L2 per P‑core.
- Product segmentation is said to add new enthusiast labels, with ‘D’ for single‑tile bLLC K‑series models and ‘DX’ for dual‑tile bLLC parts.
- Coverage frames the move as a response to AMD’s X3D chips, with 264 MB and 288 MB cache figures claimed to top the Ryzen 9 9950X3D2’s reported 208 MB, though none of this is confirmed and hints could surface at Computex in June.