Overview
- Intel said this week it has processed more than one million 300‑mm wafers on High‑NA (0.55 NA) EUV tools across installation, certification, R&D and production, and it is using the technology for select layers of its 18A (Panther Lake) chips.
- Intel reports that High‑NA patterned layers on Panther Lake meet or exceed the performance of comparable layers made with conventional 0.33‑NA EUV, and the company expanded its fleet from EXE:5000 systems to include the faster EXE:5200B.
- Current High‑NA use relies on standard 6×6‑inch masks that force large dies to be exposed as stitched half‑fields, which lowers throughput, constrains chip floorplanning and raises alignment risks for features that cross stitching boundaries.
- Intel and ASML are coordinating on a shift to 6×12‑inch reticles that would enable full‑field exposures and restore throughput, but ASML says a pilot for larger masks is planned for 2031 with high‑volume readiness targeted for 2033, so adoption will be staged.
- Wider rollout will demand major changes across mask blanks, writers, pellicles, inspection tools, handling systems and EDA flows, which could reshape supplier business and affect chip costs, capacity and design choices over the next several years.