Overview
- Multiple reports on Monday say Intel is evaluating a dual‑sided power‑delivery design for a 14A2 V2 variant that pairs its backside PowerVia/PowerDirect work with front‑side metal layers.
- The change responds to a planned shrink of the lowest metal layer pitch (M0) from about 28nm to roughly 21nm, a reduction that raises wire resistance and stresses existing through‑silicon‑via power paths.
- Dual‑sided power splits power delivery between the chip back and front so power rails have shorter, lower‑resistance paths while front‑side wiring is reclaimed for signals and clocks, which can improve performance‑per‑watt.
- Industry timelines place 14A2 risk production in 2028 and high‑volume manufacturing in 2029, a schedule that leaves Intel a narrow window to prove yields and attract customers ahead of TSMC and Samsung.
- Observers say the key signs to watch are customer tape‑outs and yield data from risk runs because those will show whether the dual‑side approach fixes voltage‑drop limits and makes 14A2 commercially viable, and tool costs such as High‑NA EUV use will affect the economics for foundry customers.