Overview
- Developed by C-DAC under MeitY’s Microprocessor Development Programme and the DIR-V initiative, the chip is presented as the third DIR-V design after THEJAS32 and THEJAS64.
- It is aimed at 5G infrastructure, automotive systems, industrial automation, consumer electronics and IoT, offering a domestically controlled option for strategic deployments.
- The core specification is a dual-core, 64-bit RISC-V CPU running at 1.0 GHz, with technical press reporting a 28 nm manufacturing node.
- Officials say it will provide a platform for startups, researchers and industry to prototype products and train talent, supporting efforts to cut reliance on foreign processors.
- C-DAC reports that quad-core successors DHANUSH64 (1.2 GHz, 28 nm) and DHANUSH64+ (2.0 GHz, 16/14 nm) are in development, with no timeframe disclosed.