Overview
- The Centre will invest ₹4,500 crore over three years from the ISM 1.0 budget to upgrade SCL, which officials say will remain in government hands.
- The plan targets roughly a 100-fold increase in wafer output with mature-node upgrades reported across 180 nm to 28 nm, including retiring the 6‑inch MEMS line.
- SCL is being positioned as a national facility where students, researchers and startups can fabricate designs, building on EDA-tool access at nearly 300 universities.
- At the Mohali event, 28 student-designed chips from 17 institutions were handed over, taking total C2S fabrications at SCL to 56, alongside new process gallery and training facilities.
- A strategic-chip drive will be led by a consortium of C-DAC, DRDO and SCL, with officials noting ISM funds are fungible and that internal work on Semicon 2.0 has begun.