Overview
- IBM announced a sub-1 nm process called NanoStack that it says reached a 0.7 nm (7 Å) node with working CMOS devices and a reported 40% SRAM area reduction.
- The company claims the design can place roughly twice the transistor density of its 2 nm chips and fit nearly 100 billion transistors on a fingernail-sized die.
- IBM published projected gains of up to 50% higher performance or up to 70% better energy efficiency versus 2 nm for designs using NanoStack.
- NanoStack stacks nanosheet transistors vertically using ultra-thin dielectric wafer bonding and layer-specific materials so each level can be optimized for n- or p-type transistors.
- Commercial rollout is uncertain because IBM develops and licenses process technology rather than running commercial fabs, it did not name production partners, and it estimates possible production in about five years while other groups pursue alternate 3D scaling approaches.