Overview
- IBM unveiled the research on Thursday, June 25, 2026, showing a 0.7 nanometer (7‑angstrom) research node built with a new three‑dimensional “nanostack” that vertically stacks and staggers nanosheet transistors.
- The company says the fingernail‑sized research die packs nearly 100 billion transistors—about twice the density of its 2 nm test chip—and reports projected gains of up to 50% higher performance or 70% lower power versus IBM’s 2 nm node.
- Researchers presented laboratory validations at VLSI 2026 that include ultra‑thin dielectric wafer bonding, dual‑channel demonstrations and working CMOS inverters, and they reported a roughly 40% improvement in SRAM cell area.
- IBM frames the result as a research milestone, not a shipping product, and says it will seek licensing and manufacturing partners for commercialization, targeting possible production in about five years contingent on process qualification and tooling.
- Widespread adoption will depend on scarce advanced equipment such as ASML’s High‑NA EUV and cooperation from toolmakers and foundries even as competitors like TSMC, Samsung and Intel push their own low‑single‑nanometer roadmaps.