Overview
- IBM announced the work on Thursday, June 25, 2026, unveiling a research prototype that packs nearly 100 billion transistors onto a fingernail‑sized die using a new three‑dimensional “nanostack” transistor architecture.
- Company data and VLSI 2026 results show the design can deliver up to 50% higher performance or 70% better energy efficiency versus IBM’s 2 nm work and about 40% smaller SRAM cell area, improvements aimed at AI and data‑center chips.
- The nanostack stacks and staggers nanosheet transistors across tiers and uses an ultra‑thin dielectric bond and dual‑channel engineering to connect layers, and IBM demonstrated functional CMOS inverters and related device validations in the lab.
- IBM is working with equipment partners including ASML, Lam Research, Tokyo Electron and SCREEN on High‑NA EUV processes but has not named a commercial foundry for the sub‑1 nm node and says production could follow in roughly five years.
- Experts and coverage note the “0.7 nm” label is a generational node name not a literal feature size, and widespread manufacture will require long material and process qualification, thermal‑budget solutions and yield scaling before commercial products reach data centers and devices.