Overview
- At the Hot Chips conference on Monday, IBM unveiled a processor design whose individual cores can natively execute both IBM z/Architecture and Arm AArch64 instructions, a first concrete hardware milestone from the April 2026 IBM–Arm collaboration.
- The disclosed design targets a 2 nanometer process with 11 high‑performance cores clocked above 5.7 GHz and a large multi‑level cache hierarchy that IBM described as optimized for transaction and data‑heavy workloads.
- IBM detailed on‑chip accelerators including AI inference engines for in‑transaction analysis, a dedicated DPU for I/O acceleration, and hardware for compression and cryptography, plus a next‑gen AI accelerator paired with high‑bandwidth HBM3e memory.
- The company said the cores implement full AArch64 semantics with SVE support and can switch execution between ISAs in nanoseconds while using Linux KVM to host Arm virtual machines, but the processor remains in development with a tape‑out reported as imminent and no commercial availability date confirmed.
- Analysts say the design could lower friction for running cloud and AI software on mainframes by opening the Arm ecosystem to Z and LinuxONE customers, yet adoption will depend on ISV porting, regulatory and customer validation, and a multi‑year product rollout; initial market reaction was modest.