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Huawei Unveils Tau Scaling Law and LogicFolding, Sees Path to 1.4nm‑Equivalent Chips by 2031

The firm says the design‑first approach can reduce dependence on EUV lithography and change how China pursues high‑end chips.

Overview

  • Huawei presented the Tau (τ) Scaling Law and LogicFolding architecture at the IEEE ISCAS conference in Shanghai on Monday, May 25, 2026, and said Kirin smartphone chips using the design will ship in autumn 2026.
  • The Tau Scaling Law shifts focus from shrinking transistors to shortening signal travel time across circuits and systems to boost effective transistor density.
  • LogicFolding is a stacked, folded circuit layout that Huawei says cuts resistive and capacitive signal load and has been used in what the company calls 381 mass‑produced chip designs over six years.
  • Independent verification is missing and analysts warn major engineering hurdles remain, including heat and power management, production yield, EDA tool and fabrication ecosystem gaps, and system‑level integration before matching true 1.4nm node performance.
  • Markets reacted positively with gains in some Chinese chip stocks and analysts say the move could narrow China’s hardware gap and reshape procurement for AI and smartphones if Huawei’s autumn Kirin launch delivers measurable, third‑party benchmarks.