Overview
- Huawei, which announced the plan on Monday, set a goal to reach transistor densities it says are equivalent to a 1.4‑nanometer class by 2031 and pledged to ship Kirin processors using the approach as early as autumn 2026.
- The company described a new design principle called the 'Tau Scaling Law' that focuses on cutting signal and data path times and a stacked‑logic method called LogicFolding to reduce energy use and boost clock speeds.
- Huawei also claimed it has designed and mass‑produced 381 chips under this principle over the past six years, a claim that the company has not yet supported with independent benchmarks or system‑level tests.
- Analysts and industry reporting note major hurdles remain, including higher costs, greater power draw, tougher thermal management in small devices like phones, and limits on China’s access to ASML’s newest EUV machines.
- The announcement positions Huawei to try to narrow the gap with leaders such as TSMC, which targets a 1.4‑nanometer process around 2028, but independent verification and real‑world performance will determine whether the approach can match conventional scaling.