Overview
- This week EPFL published a peer‑reviewed account and press briefings describing LogSync, a fabricated 32‑channel SoC that was validated on human intracranial datasets and tested in live rats for phase‑locked stimulation.
- The chip was made in 65‑nm CMOS, occupies about 5.46 mm², uses custom logarithmic arithmetic and on‑chip neural models, and reports energy use near 6.14 μW per channel with a total system budget under roughly 200 μW.
- On human iEEG data the device-extracted features—oscillatory power and phase synchrony—supported classifiers with task‑specific sensitivity and specificity for cognitive engagement and emotional arousal.
- In vivo work at the University of Minnesota confirmed the SoC can track ongoing oscillations and issue stimulation triggers locked to neural phase, and the team presented related self‑supervised ML research at ICML 2026.
- Funded by a CHF 6.6 million NIMH program and moving toward commercial development via EPFL spin‑off Infera Neuro, the project still needs longitudinal human trials, regulatory integration with clinical stimulators, and broader patient validation before clinical use.