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D-Wave Unveils Gate-Model Roadmap to 100 Logical Qubits by 2032

It relies on a superconducting dual-rail design with built-in error detection to try to speed development of fault-tolerant quantum computers.

Overview

  • D-Wave presented a staged gate-model roadmap at its Investor Day on Monday, June 1, 2026 that plots hardware milestones from a 17-physical-qubit device in 2026 to a 100-logical-qubit system by 2032.
  • The company says its dual-rail superconducting qubits include on-chip error detection that can identify roughly 90% of errors and that, with error detection, it has demonstrated two-qubit fidelities of 99.9%.
  • D-Wave is targeting a Lambda value of 10, which it describes as a measure of how quickly errors fall as more error correction is added, and it claims superconducting error-correction cycles can run 100 to 1,000 times faster than neutral-atom or trapped-ion approaches.
  • The roadmap links intermediate physical-qubit builds (17, 49, 181) to progressive error-reduction goals and to early commercial aims such as quantum chemistry and quantum AI, but the schedule and technical targets are forward-looking and carry execution risk.
  • Investors gave a muted response with QBTS trading down in premarket action and analysts remain cautiously positive, while the plan builds on D-Wave’s 15-year annealing business and its recent acquisition of Quantum Circuits to accelerate gate-model work.