Overview
- Broadcom’s design stacks two dies to tighten interconnects for faster data movement and is intended to cut power use, with the company claiming around 10x better energy performance versus traditional designs.
- Fujitsu is producing engineering samples now for a data center chip that TSMC is fabricating by fusing a 2-nanometer die with a 5-nanometer die.
- Two additional stacking-based products are slated to ship in the second half of 2026, with three more designs planned for sampling in 2027.
- The 1 million-unit goal spans multiple designs beyond Fujitsu as Broadcom extends the approach across its custom-silicon programs.
- Broadcom projects about $8.2 billion in AI chip revenue for its first fiscal quarter, roughly double from a year earlier.