Overview
- AMD disclosed on May 21 that it has begun volume ramp of its 6th‑Gen EPYC processor codenamed Venice on TSMC’s 2nm node in Taiwan and plans a subsequent ramp at TSMC’s Arizona fab.
- The company committed more than $10 billion to partners across Taiwan to expand advanced packaging, substrates and ODM capacity for 2.5D Elevated Fanout Bridge interconnects and panel-based packaging.
- AMD said its Helios rack, which pairs Venice CPUs with Instinct MI450X GPUs, remains on track for multi-gigawatt deployments beginning in the second half of 2026.
- CEO Lisa Su tied the program to rapidly rising AI inferencing and agentic workloads and said AMD expects CPU supply to increase quarter over quarter through 2026.
- Key risks to execution include packaging capacity, yield and geopolitical constraints that could delay rack rollouts and test AMD’s plan to diversify production between Taiwan and the U.S.